PULSAR IP Core

Scalable, programmable DSP co-processor

PULSAR Digital Signal Processing (DSP) IP Core is a scalable, programmable co-processor that is optimized for PHY-layer designs and provides parallel processor architecture for signal processing electronic circuits. HW/SW optimized, the patented co-processor perfectly allies hardware computational power with the flexibility of software and thus ensures customer products to be evolutive, easy to customize and extend.  

Scalable

PULSAR hardware is scalable, enabling to optimise the system depending on the cost, performance and power consumption constraints imposed by the application.

  • Hardware complexity can be adapted to the application to manage different levels of system complexity (long/short range, high/low throughput ...)
  • Highly parallel SIMD (single instruction multiple data) processor architecture
  • Low power solution. Specialised hardware operator to reduce power consumption, adapted to customers' data-rate requirements
  • Can be optimized for FPGA and ASIC targets. Easy migration from FPGA to ASIC. FPGA prototyping before tape-out

Programmable

PULSAR Hardware is programmable, resulting in a highly flexible Software-defined Radio technology platform.

  • Flexible signal processing circuits with reduced development effort (20x lower than hard-wired design)
  • Easy product maintenance
  • Easy support of standard revisions
  • Easy design of multi-standard multi-protocol applications (4G/LTE, 5G, LORA, Mbus, SIGFOX, DVB-T2, DVB-S2, …)

From IP block to complete electronic board

PULSAR DSP IP Core is available as Intellectual Property (IP) block for FPGA or ASIC. PULSAR DSP IP blocks help Original Equipment Manufacturers (OEM) quickly develop and implement reliable signal processing IP Cores and generate highly flexible and powerful components for their application-specific integrated circuits (ASICs).

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